November 27, 2020

PCB design: how to reduce errors and increase efficiency

Board design is a critical and time-consuming task, and any problem requires engineers to examine the entire design on a network-by-component basis. It can be said that the design requirements of the board are as good as the chip design.

A typical board design flow consists of the following steps:

The first three steps take the most time because the schematic check is a manual process. Imagine a SoC board with 1000 or more connections. Manually checking each connection is a tedious task. In fact, it is almost impossible to check each connection, which can lead to problems with the final board, such as incorrect wiring, floating nodes, and so on.

The schematic capture phase generally faces the following types of problems:

● Underscore error: such as APLLVDD and APLL_VDD

● Capitalization issues: such as VDDE and vdde

●Spelling mistakes

●Signal short circuit problem

●...and many more

To avoid these errors, there should be a way to check the complete schematic in a matter of seconds. This method can be implemented with schematic simulation, which is rarely seen in the current board design flow. Schematic simulation allows you to see the final output at the desired node, so it automatically checks for all connection problems.

The following is explained by a project example. Consider a typical block diagram of a board:

figure 1

In complex board designs, the number of connections can reach thousands, and very few changes are likely to waste a lot of time checking.

Schematic simulation not only saves design time, but also improves board quality and increases overall process efficiency.

A typical device under test (DUT) has the following signals:

figure 2

The device under test will have various signals after some pre-adjustment, and there are various modules, such as voltage regulators, op amps, etc., for signal adjustment. Consider an example of a power supply signal obtained by a voltage regulator:

Figure 3: Schematic of the sample board.

In order to verify the connection and perform an overall check, a schematic simulation was used. Schematic simulation consists of schematic creation, test platform creation, and simulation.

During the test platform creation process, an excitation signal is sent to the necessary input, and then the output is observed at the signal point of interest.

The above process can be implemented by connecting a probe to a node to be observed. The node voltage and waveform can indicate if there is an error in the schematic. All signal connections are automatically checked.

Figure 4: Schematic test platform and simulation values ​​for each node.

Let's take a look at a part of the above picture where the nodes and voltages detected are clearly visible:

So with the help of simulation, we can directly observe the results and confirm that the schematic of the board is correct. In addition, a survey of design changes can be made by carefully adjusting the stimulus signal or component values. Schematic simulation can therefore save board design and inspectors a lot of time and increase the chances of design correctness.

Standard Recovery Stud Diode are mainly used for rectifying and switching

It has positive pressure reduction (0.4v -- 1.0v), short reverse recovery time (2-10ns nanosecond), large reverse leakage current, low pressure resistance, generally lower than 150V, and is used in low voltage situations.

Diodes are electronic devices that have two electrodes that allow only a single current to flow in a single direction.Varicap bond (bond) is an electronic adjustable capacitor.Most diodes have a current orientation that we call reading "rectifier".The most common function of a diode is to allow only the current to pass in one direction (called forward bias) and to block in the opposite direction (called reverse bias).

Standard Recovery Stud Diode

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