Experienced power developers know that EMI suppression during PCB design can save a lot of time in the final process for EMI suppression. This article will explain the standard steps in EMI design in PCB. Interested friends can take a look. IC power processing Ensure that each IC's power PIN has a 0.1UF decoupling capacitor. For BGACHIP, there are 8 capacitors of 0.1UF and 0.01UF at the four corners of the BGA. Pay special attention to the power supply of the trace, such as VTT. This not only has an impact on stability, but also has a great impact on EMI. Clock line processing 1) It is recommended to take the clock line first. 2) For clock lines with a frequency greater than or equal to 66M, the number of vias should not exceed 2, and the average should not exceed 1.5. 3) For clock lines with a frequency less than 66M, the number of vias should not exceed 3, and the average should not exceed 2.5. 4) For clock lines longer than 12 inches, if the frequency is greater than 20M, the number of vias must not exceed two. 5) If there is a via in the clock line, add a bypass capacitor between the second layer (ground layer) and the third layer (power plane) adjacent to the via, as shown in Figure 2.5-1, to ensure After the clock line is changed, the loop of the high frequency current of the reference layer (adjacent layer) is continuous. The power supply layer where the bypass capacitor is located must be the power supply layer through which the vias pass, and as close as possible to the vias. The bypass capacitor should be spaced no more than 300 mils from the vias. 6) All clock lines cannot be worn on the island in principle. The following are four examples of island wear. The cross-island appears between the power island and the power island. At this point, the clock line is routed on the back side of the fourth layer, the third layer (power layer) has two power islands, and the fourth layer of traces must cross the two islands. The island is between the power island and the island. At this time, the clock line is routed on the back side of the fourth layer, and a ground island is located in the middle of a power island of the third layer (power layer), and the trace of the fourth layer must cross the two islands. Inter-island occurs between the island and the stratum. At this time, the clock line is routed in the first layer, and there is a ground island in the middle of the second layer (ground layer), and the trace of the first layer must cross the island, which is equivalent to the ground line being interrupted. There is no copper under the clock line. If the conditional limit is not enough to prevent the island from being worn, ensure that the clock line with a frequency greater than or equal to 66M does not pass through the island. If the clock line with a frequency less than 66M passes through the island, a decoupling capacitor must be added to form a mirror path. Taking Figure 6.1 as an example, place a 0.1UF capacitor between the two power islands and close to the clock line across the island. When facing the two vias and the one-time trade-off, choose to wear the island once. Keep the clock line away from the edge of the I/O side of the board 500 MIL or more, and do not walk with the I / O line. If you can't do it, the clock line and I / O line line spacing should be greater than 50 MIL. When the clock line is on the fourth layer, the reference layer (power plane) of the clock line should be as far as possible for the power supply surface of the clock. The less the clock is referenced by other power planes, the better the clock is greater than or equal to 66M. The line reference power plane must be a 3.3V power plane. When the clock line is wired, the line spacing is greater than 25 MIL. The line that goes in when the clock line is wired and the line that goes out should be as far as possible. Try to avoid the wire bonding method similar to that shown in Figure A and Figure C. If the clock wire needs to be changed, avoid the wire drawing method of Figure E, and use the wire drawing method of Figure F. When the clock line is connected to a device such as BGA, if the clock line is changed, try to avoid the trace form of Figure G. Do not use the trace under the BGA. It is better to use the trace form of Figure H. Pay attention to each clock signal, don't ignore any clock, including AC_BITCLK of AUDIOCODEC, especially pay attention to FS3-FS0. Although it is not a clock from the name, it actually runs the clock, so pay attention. The ClockChip pull-up resistor is as close as possible to the ClockChip. I/O port processing Each I/O port includes PS/2, USB, LPT, COM, SPEAKOUT, and GAME divided into one piece. The leftmost and rightmost are connected to the digital ground. The width is not less than 200 MIL or three vias. Do not connect to digital ground elsewhere. . If the COM2 port is pin-type, as close as possible to the I/O ground. The I/O circuit EMI device is as close as possible to the I/OSHIELD. The power supply layer and the ground layer at the I/O port are separately islanded, and the Bottom and TOP layers are laid on the ground. The signal is not allowed to pass through the island (the signal line is directly pulled out of the PORT, not in the I/OPORT long distance). Some notes A. For EMI design specifications, design engineers must strictly abide by, EMI engineers have the power to inspect, and lead to EMI test FAIL in violation of EMI design specifications, responsibility is borne by the design engineer. B. EMI engineers are responsible for design specifications, and strictly comply with EMI design specifications, but still EMI testing FAIL, EMI engineers are responsible for giving solutions and summarizing them into EMI design specifications. C. EMI engineers are responsible for EMI testing of each peripheral port and should not be missed. D. Each design engineer has the right to propose and challenge the design specification. The EMI engineer is responsible for answering the query, and the engineer's suggestion is confirmed by the experiment and then added to the design specification. E.EMI engineers have a responsibility to reduce the cost of EMI design and reduce the number of beads used.
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