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Data acquisition design of betting machine based on TMS320F2812 and ADS8365
With the rapid development of China's Welfare Lottery business, the computer lottery sales system has placed higher demands on the control of betting machine operations and the collection of telemetry data. As a key component for real-time monitoring and control of the Fucai sales system, data acquisition has played a crucial role. However, during the process of data acquisition, interference factors such as harmonics can significantly affect the accuracy and speed of analog signal collection from each module in the betting machine, making this an important research topic.
In recent years, the performance of various integrated DSPs has greatly improved, while their prices have dropped significantly. More and more users are now adopting DSP devices to enhance product performance. This paper presents a signal acquisition circuit designed using ADS8365 and TMS320F2812. The interface is simple, the acquisition precision is high, and the speed is fast, meeting the expected design goals.
**1. Introduction to TMS320F2812**
TI (Texas Instruments) promotes the TMS320F2812, a 32-bit fixed-point microcontroller unit (MCU) with a frequency of up to 150MHz. It features multiple bus interfaces including I2C, SPI, CAN, and PWM, making it suitable for various industrial control applications. The device offers high performance, portability, and is ideal for use in handheld devices. It also meets rigorous environmental testing standards, ensuring reliability in industrial settings.
**2. Introduction to ADS8365**
ADS8365 is a high-speed, low-power, 6-channel simultaneous sampling analog-to-digital conversion chip that operates on a single +5V power supply. It supports a maximum sampling rate of 5MHz, with 80dB common-mode rejection and six differential sample-and-hold amplifiers. The chip includes a 2.5V reference and a high-speed parallel interface, making it ideal for precise and fast data acquisition.
**3. Interface Circuit Design between ADS8365 and TMS320F2812**
As both ADS8365 and TMS320F2812 are high-speed chips from TI, they can be perfectly matched in terms of speed, enabling seamless communication between them. The PTout analog signal, ranging from -5V to +5V, is input through a differential circuit into the A0 channel of ADS8365. The interface selects a 16-bit data output mode, so the BYTE and ADD pins of ADS8365 are grounded. The reading of each channel’s conversion result is controlled by address lines A2, A1, and A0.
The chip select signal for ADS8365 is generated by F2812 using address lines A15, A14, A13, and the I/O space chip select line XZCS#, via a 74LV138 decoder. The ADS8365 occupies the lower 32K address space of the F2812 I/O space, and the debug process is independent of the running address.
To achieve simultaneous sampling across all six channels of ADS8365, the HOLDA#, HOLDB#, and HOLDC# control signals are connected to the same I/O pin of F2812. When this pin is activated, all six channels are triggered simultaneously. The clock signal for ADS8365 is provided by the T4PWM output of Timer 4 in F2812 at a frequency of 3.75MHz. The A/D chip is also reset when the DSP is reset. The end-of-conversion signal (EOC#) is connected to the external interrupt pin XINT2 of the DSP, allowing the A/D results to be read via either interrupt or polling methods, depending on application needs.
ADS8365 is powered by +5V analog (AVDD) and digital (DVDD) supplies, while its internal buffer uses the same +3.3V voltage as the F2812. The buffer voltage (BVDD) allows direct connection to 3V or 5V systems. Since the F2812’s I/O voltage is +3.3V, the BVDD of the ADS8365 must be set to 3.3V.
**4. TMS320F2812 Configuration**
(1) Conversion Clock Setting: In this system, the PWM signal from F2812 provides the clock for ADS8365. PWM2 is configured in full-comparison mode with active-high output. With a system clock of 90MHz, the high-speed peripheral clock (HSPCLK) is set to 45MHz. By setting the general-purpose timer T1 period register (T1PR) to 12 and compare register (T1CMPR) to 6, the output clock frequency becomes 3.75MHz, matching the maximum clock frequency required by ADS8365.
(2) Output Port Setup: PWM1/GPIOA0 and PWM3/GPIOA2 are configured as GPIO outputs. GPIOA0 controls the RESET# signal of ADS8365, while GPIOA2 controls the HOLDA#, HOLDB#, and HOLDC# signals. The XINT2_ADCSOC pin on Port E is set as an interrupt input.
At the end of the ADS8365 conversion, the EOC# pin goes low, triggering the XINT2# interrupt. The interrupt service routine then reads the data. When the chip select (CS#) of ADS8365 is high, the parallel data output D[15:0] is in a high-impedance state. When CS# is low, the data bus reflects the current state of the output buffer. To properly read the parallel bus, CS# must be set low. The XZCS2# of the F2812 is used as the chip select signal for ADS8365, mapping the ADS8365 address to the extended memory space XINTF Zone2 of the F2812. The A9, A5, and A3 output pins of the F2812 are used to control the A0–A2 address lines of the ADS8365, as shown in Table 1.
**5. Data Acquisition Process**
The read pointer is initialized by pulling the RESET# pin of ADS8365 low. GPIOA0 controls the RESET# pin. During system initialization, GPIOA0 starts high and is pulled low once the system clock stabilizes, ensuring the ADC outputs data in the order of channels A0, A1, B0, B1, C0, C1.
The HOLDX# signal is an active-low trigger for data acquisition. Once HOLDX# remains low for at least 20ns, the conversion begins. By connecting all three HOLD signals to GPIOA2, the sample-and-hold amplifiers of each channel are triggered simultaneously, allowing all channels to start conversion at the same time.
When the conversion result is stored in the output register, the EOC# pin remains low for half a clock cycle. By setting RD# and CS# to low, data can be read from the parallel output bus. Read (RD#) and write (WR#) are active-low signals. When CS# is low, the ADS8365 output buffer updates on the falling edge of RD#. Thus, the RD# signal must be triggered before each read sequence to ensure new data is available. The timing diagram for reading ADS8365 is shown in Figure 2.
**6. Software Design**
To facilitate debugging and maintenance, the software follows a modular, top-down approach, combining C and assembly language programming. After power-on reset, the system boots the loader based on the selected mode, jumps to the main program entry, and initializes variables, data buffers, control registers, and status registers. After resetting and initializing the external ADS8365, the system waits for an external interrupt. The A/D converted data is read into the allocated data buffer within the interrupt service routine.
As a fixed-point DSP, the F2812 improves operation accuracy and speed by utilizing the IQmath Library provided by TI, enabling a seamless interface between floating-point arithmetic and fixed-point code. This simplifies development and enhances the real-time performance of the program. An example of the main code is as follows:
```c
void main(void)
{
ptrCHA0 = (int*)CHA0;
InitSysCtrl();
InitGpio();
ResetADS8365();
DINT;
PieCtrlRegs.PIEIER1.bit.INTx5 = 1;
XIntruptRegs.XINT2CR.all = 0x0000;
read_A();
XIntruptRegs.XINT2CR.all = 0x0001;
PieCtrlReg.PIEACK.all = 0x0001;
return;
}
```
Applications: aerospace, electronics, automotive, construction, medical...Applications: aerospace, electronics, automotive, construction, medical...Applications: aerospace, electronics, automotive, construction, medical...