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Data acquisition design of betting machine based on TMS320F2812 and ADS8365
With the rapid growth of China's Welfare Lottery business, the computerized lottery sales system has placed higher demands on the control of betting machine operations and the collection of telemetry data. As a fundamental part of real-time monitoring and control of the Fucai sales system, data acquisition plays a crucial role. However, during the process of data collection, challenges such as harmonic interference make it difficult to accurately and quickly capture analog signals from each module in the betting machine, making this an important research focus.
In recent years, the performance of various integrated DSPs has significantly improved, while their costs have dropped considerably. More users are now adopting DSP devices to enhance product performance. This paper presents a signal acquisition circuit designed using ADS8365 and TMS320F2812. The circuit features a simple interface, high precision, and fast acquisition speed, meeting the expected design goals.
**1. Introduction to TMS320F2812**
TI's TMS320F2812 is a 32-bit fixed-point microcontroller with a maximum frequency of 150MHz. It offers multiple bus interfaces including I2C, SPI, CAN, and PWM, making it suitable for various industrial control applications. It is known for its high performance, portability, and ability to operate under extreme temperatures and vibrations, making it ideal for industrial environments.
**2. Introduction to ADS8365**
The ADS8365 is a high-speed, low-power, six-channel simultaneous sampling analog-to-digital converter that operates on a single +5V supply. It supports a maximum sampling rate of 5MHz, with 80dB common-mode rejection and six differential sample-and-hold amplifiers. The chip also includes a 2.5V reference and a high-speed parallel interface, making it well-suited for high-precision applications.
**3. Interface Circuit Design Between ADS8365 and TMS320F2812**
As both the ADS8365 and TMS320F2812 are high-speed chips from TI, they can be perfectly matched in terms of speed, ensuring seamless communication between them.
The PTout signal, which is an analog input ranging from -5V to +5V, is connected to the A0 channel of the ADS8365 through a differential circuit. The interface is set to 16-bit mode, so the BYTE and ADD pins of the ADS8365 are grounded. The address lines A2, A1, and A0 are used to select the conversion result for each channel. The chip select signal (CS#) of the ADS8365 is generated by combining the F2812's address lines A15, A14, A13, and the I/O space chip select line XZCS#, using a 74LV138 decoder. The ADS8365 occupies the lower 32K address space of the F2812’s I/O space, allowing for independent debugging.
To enable simultaneous sampling of all six channels, the HOLDA#, HOLDB#, and HOLDC# control signals of the ADS8365 are connected to the same I/O pin of the F2812. When this pin is activated, all six channels can be sampled simultaneously.
The clock signal for the ADS8365 is provided by the T4PWM output of Timer 4 in the F2812 at 3.75MHz. The A/D chip is reset along with the DSP. The end-of-conversion (EOC#) signal is connected to the external interrupt pin XINT2 of the DSP, enabling the system to read the conversion results either via interrupts or polling, depending on the application requirements.
The ADS8365 is powered by +5V for both analog (AVDD) and digital (DVDD) supplies, while its internal buffer uses +3.3V, matching the F2812’s I/O voltage. Therefore, the BVDD of the ADS8365 must be set to 3.3V when used with the F2812.
**4. TMS320F2812 Configuration**
(1) Clock Setting: In this system, the PWM signal from the F2812 is used to drive the ADS8365. PWM2 is configured in full comparison mode with an active-high output. With a system clock of 90MHz, the high-speed peripheral clock (HSPCLK) is set to 45MHz. The general-purpose timer T1 is set to a period register value of 12 (T1PR=0x000c) and a compare register value of 6 (T1CMPR=0x0006), resulting in an output clock frequency of 3.75MHz, which matches the maximum clock requirement of the ADS8365.
(2) Output Port Setup: PWM1/GPIOA0 and PWM3/GPIOA2 are configured as GPIO outputs. GPIOA0 controls the RESET# signal of the ADS8365, while GPIOA2 controls the HOLDA#, HOLDB#, and HOLDC# signals. Port E's XINT2_ADCSOC is set to an external interrupt input.
When the ADS8365 completes a conversion, the EOC# pin goes low, triggering the XINT2# interrupt. The interrupt service routine then reads the data. When the chip select (CS#) is high, the parallel output pins D[15:0] are in a high-impedance state. When CS# is low, the data is available on the bus. To ensure proper reading, the CS# must be pulled low. Since the F2812’s XZCS2# is used as the chip select for the ADS8365, the ADS8365’s address is mapped to the extended memory space (XINTF Zone2) of the F2812. The F2812’s A9, A5, and A3 pins are used to control the ADS8365’s A0–A2 address lines.
**5. Data Acquisition Process**
The read pointer is initialized by pulling the ADS8365’s RESET# pin low. The RESET# pin is controlled by GPIOA0. During initialization, GPIOA0 starts high and is pulled low once the system clock stabilizes, ensuring that the ADC outputs data in the order of A0, A1, B0, B1, C0, C1.
The HOLDX# signal, which is an active-low sampling trigger, initiates the conversion when held low for at least 20ns. By connecting all three HOLD signals to GPIOA2, all channels are sampled simultaneously, ensuring synchronized conversion across all six channels.
Once the conversion is complete, the EOC# pin remains low for half a clock cycle. By setting RD# and CS# to low, the data can be read from the parallel output bus. Both RD# and WR# are active-low signals. When CS# is low, the output buffer of the ADS8365 updates on the falling edge of RD#. Therefore, the RD# signal must be triggered before each read sequence to ensure that the latest data is read. The timing diagram for this process is shown in Figure 2.
**6. Software Design**
To facilitate debugging and maintenance, the software follows a modular, top-down, and gradually refined approach. It combines C and assembly language programming. After power-on reset, the system boots the loader based on the selected mode, jumps to the main program entry, and initializes variables, data buffers, control registers, and status registers. After resetting and initializing the external ADS8365, the system waits for an external interrupt. The A/D conversion results are read into the allocated data buffer within the interrupt service routine.
The F2812 is a fixed-point DSP, and to improve accuracy and speed, the software makes full use of TI’s IQmath Library, enabling a seamless interface between floating-point arithmetic and fixed-point code. This simplifies development and greatly enhances the real-time performance of the program. An example of the main code is as follows:
```c
void main(void)
{
ptrCHA0 = (int*)CHA0;
InitSysCtrl();
InitGpio();
ResetADS8365();
DINT;
PieCtrlRegs.PIEIER1.bit.INTx5 = 1;
XInterrupRegs.XINT2CR.all = 0x0000;
read_A();
XInterrupRegs.XINT2CR.all = 0x0001;
PieCtrlReg.PIEACK.all = 0x0001;
return;
}
```
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