LTE is the next-generation 3G UMTS wireless protocol developed by 3GPP. The purpose is to make the cellular network a packet-based all-IP network. Among the various indicators of LTE, the most prominent are higher downstream and upstream data rates (100Mbps and 50Mbps, respectively) and low packet delays (no more than 5ms), and the delays are new services such as wireless VoIP more and more important. In addition, the technology must also provide greater spectral efficiency, greater capacity, and lower communication cost per bit. The multiple concepts used by LTE in achieving these goals will greatly increase the complexity of the technology. Like other cutting-edge technologies, these concepts include more complex modulation schemes in the downstream and upstream directions, flexible channel bandwidth, and MIMO architecture, which requires multiple antennas in some cases. In addition, the increased complexity of LTE will require base stations and mobile phones to have very powerful, flexible, and innovative processing capabilities. LTE adopts the OFDM (Orthogonal Frequency Division Multiplexing) modulation scheme in the downlink direction, and the uplink adopts the SC-FDMA (Single Carrier Frequency Division Multiple Access) scheme derived from OFDM. The uplink uses SC-FDMA because its power amplifier efficiency is higher than OFDM, which can extend the battery life of mobile phones. OFDM is quite complicated. It uses 2048 subcarriers with a pitch of 15 kHz. Such a large number of subcarriers enhances the multipath capability of OFDM, which in turn improves its anti-interference ability, spectrum efficiency and data rate. Both the downlink and uplink directions have adjustable bandwidth from 1.25MHz to 20MHz, thus allowing LTE to use new and existing frequency bands. The MIMO architecture helps LTE achieve high data rates through multiple signal paths. However, it needs to be reiterated that in order to control the cost of LTE mobile phones, the modulation schemes used in LTE downlink and uplink are slightly different. If the mobile phone is equipped with multiple antennas, MIMO has the potential to increase the data rate to more than 100 / 50Mbps. Equipping LTE base station with multi-core DSP To meet the high complexity requirements of LTE, TI has developed the TCI6487 multi-core DSP with embedded accelerator. These accelerators can meet various 2G, 3G, and 4G wireless base station standards used in baseband processing. TCI6487 is the industry's first multi-core DSP with three "C64 + DSP cores", which can provide up to 3GHz DSP processing power and can fully handle LTE baseband tasks such as MAC and PHY processing. In order to achieve the higher data rate of LTE and ensure that the packet delay is less than 5ms, TCI6487 uses Viterbi and Turbo Coprocessor (TCP) to share the encoding / decoding load of the main DSP core. These co-processing accelerators can handle many of the computationally intensive coding functions required for LTE to function properly. Specifically, TCP2 as a flexible accelerator can support Turbo decoding; it not only supports LTE, but also supports all 3GPP series standards. Offloading the Turbo decoding function from the TCI6487 DSP core can free up more processing power for MAC and PHY processing, or the effective processing margin can be used to handle more users in particularly high-density cellular base stations. If the base station is to meet the higher requirements of LTE, a certain degree of flexibility and reconfiguration capabilities are important. For example, in low-density cellular networks, TCI6487 can be used as a single-chip solution, where one core is dedicated to MAC processing and the other two perform PHY layer transceiver functions. Many high-density cellular networks will present different challenges in order to take full advantage of LTE's higher data rates. In this case, multiple TCI6487 solutions can be used, in which one chip performs MAC processing for all cells, while the other chips are used to handle PHY transceiver tasks. In this way, DSP can be used specifically for OFDM or SC-FDMA modulation schemes implemented in LTE downlink and uplink modes. To take advantage of the inherent flexibility of multi-core devices, a multi-level on-chip memory architecture is required. For TCI6487, L1 memory can be configured as cache or standard storage. In addition, the amount of secondary memory dedicated to each core can be adjusted. A total of 3MB of L2 memory can be evenly distributed among the three cores, or the three cores are allocated 0.5, 1, and 1.5MB in sequence. When multiple different processing requirements occur at the same time, this method will affect the efficiency of a complex LTE deployment. For example, a kernel that is processing a task with high memory requirements may be allocated 1.5MB of secondary memory. Keep pace with the development of LTE To avoid bottlenecks, transmitting data through the base station at the LTE rate requires very high-speed I / O for DSP data input and output. Therefore, the peripherals on the TCI6487 include a serial RapidIO (SRIO) interface. SRIO can expand the flexibility and scalability of the device to the board level, thereby reducing the complexity and cost of the circuit board. Each channel on this dual-channel SRIO interface can achieve a data rate of 1.25, 2.5, or 3.125 Mb (Gbps) per second. This SRIO interface can be configured as two single-channel high-speed dedicated links, used to connect ASIC or FPGA devices on the circuit board, or connect to the circuit board on the back panel of the LTE base station. In another configuration, SRIO can be used to interconnect multiple DSPs in a peer-to-peer or master-slave architecture. When configured as an on-board peer-to-peer connection between chips, this dedicated SRIO channel can eliminate bottlenecks encountered when the shared bus is overloaded. Because LTE can transmit large amounts of data, this feature becomes very important. The scalability and flexibility of the SRIO interface helps to implement various architectures, including star, ring, U-shaped daisy chain, etc. (see Figure 1). Another option for inter-chip interconnection on LTE base stations is the Gigabit Ethernet switching matrix. In order to achieve this function, TCI6487 also integrates a Gigabit Ethernet interface. Antenna interface In the slower 3G and 3.5G protocol implementations, the DSP can connect the antenna data stream through an external memory interface (EMIF) on the ASIC or FPGA. However, the higher transmission speed and lower packet delay in the 4G LTE specification require next-generation antenna solutions. Fortunately, there are at least two industry-standard antenna interfaces that can meet the speed requirements of LTE, including the Common Public Radio Interface (CPRI0) and Open Base Station Architecture Organization (OBSAI) interfaces. The link rate of CPRI ranges from 614.4Mbps to 2.4Gbps; the rate of OBSAI ranges from 768Mbps to 3.07Gbps. Due to the high data rates of CPRI and OBSAI, LTE antenna data streams can be routed directly to the baseband processor, eliminating the need to use ASICs or FPGAs that are commonly used to connect antenna data to DSPs (see Figure 2). TI's TCI6487 chip integrates a six-channel antenna interface and is the first DSP that can support both CPRI and OBSAI standards. In addition, this six-channel OBSAI / CPRI antenna interface can be used to configure many architectures on the circuit board, such as star, ring, U-shaped daisy chain, standard daisy chain, etc. (see Figure 3). Each antenna interface link can support uplink or downlink mode, and can support up to 48 uplink and 24 downlink data streams. Software Environment Some infrastructure OEMs are using multiple TCI6487 multi-core DSP devices to develop flexible multi-standard baseband cards. This platform allows flexible implementation, which is very important for the original LTE platform used in the laboratory or field trials. Infrastructure vendors like to advocate multi-standard platforms because using a single hardware platform to support multiple standards can reduce R & D investment and accelerate time-to-market. Some infrastructure vendors are using TCI6487 multi-core DSP to develop platforms that can support WCDMA-HSPA and LTE, and some vendors are developing platforms that can support WiMAX and LTE. An easy-to-implement and fully tested LTE software module library supports TCI6487 DSP, which will shorten the time to market for new base stations. All PHY functions of LTE, including modulation mapping, scrambling code, channel equalization, RACH processing, etc., have been implemented in product development and can be used as library modules. In addition, its compatibility with TI's previous generation wireless infrastructure DSP means that many common functions in 3G and 3.5G WCDMA protocols can be seamlessly ported to LTE applications. The software development tools used for TI's previous generation DSP, such as Code Composer Studio, can also be used for the TCI6487 chip, thus providing developers with a familiar and efficient software development tool suite. The addition of the Linux development environment provided by Virtual Logix, a third-party vendor of TI, has further simplified the programming of TCI6487. Virtual Logix's Linux kernel running with DSP / BIOS provides an efficient environment that can be used to quickly develop MAC and PHY programming algorithms and other software modules used by LTE. There are also hardware development platforms provided by third-party vendors, such as CommAgility's AMC-6487 platform with three TCI6487s, which can also be used to advance development speed. Reduce power consumption Power consumption is a basic factor that wireless base stations need to consider. Higher power consumption will increase the operating costs of service providers. Without meeting the power consumption conditions of the base station, it is impossible to meet the requirements of LTE to reduce the communication cost per bit. Therefore, compared with discrete DSPs where each DSP has its own peripheral interface, the multi-core DSP TCI6487 can significantly save power consumption. By integrating multiple I / O interfaces with three DSP cores on one chip, a multi-core DSP can save power consumed by peripheral interfaces because these interfaces can be shared by more than one DSP core. In addition, TI's SmartReflex energy-saving technology is also implemented in the TCI6487 device. In addition to traditional energy-saving methods, such as power switching, isolation, and voltage transfer, which divide the power domain of the device through granular technology, SmartReflex technology also allows designers to simultaneously reduce static and dynamic power consumption while still meeting LTE performance requirements. SmartReflex technology considers factors such as silicon characteristics of special devices based on manufacturing process and thermal parameters. This approach can effectively reduce the power of the DSP while maintaining the TCI6487's 1GHz performance target. According to the algorithm used, TCI6487 can become a DSP with particularly high efficiency, and its power consumption can be limited to 6W. Such low power characteristics allow the use of 6 to 8 devices on a single card without breaking through the power budget. This configuration supports a key goal of infrastructure vendors to support 3 sector (or cellular) LTE baseband processing on a single hardware card.
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Figure 1: SRIO supports various peer-to-peer configurations including U-shaped daisy chains. 
Figure 2: Basic 3G or 3.5G antenna architecture. 
Figure 3: The latest antenna architecture based on CPRI or OBSAI allows direct connection to the backplane.
New DSP helps base station equipment meet and exceed LTE requirements
LTE is a 4G solution that the wireless industry will mainly promote in the next few years. It has many extremely high-performance goals. These goals will bring many difficult challenges to technology providers, equipment manufacturers and service providers.