This article refers to the address: http:// With the development of digital video and image processing, digital audio technology is also improving, especially ISO/IEC-based MPEG technology. MP3 is an abbreviation of MPEGAudioLayerIII, which is an international standard for Hi-Fi level audio compression. At present, MP3 decoding on the market is basically using dedicated chip decoding, using a dedicated chip to decode large volume, and supporting audio formats are limited. We use soft decoding in C language on DSP chip. Soft decoding is flexible, portability is good, easy to upgrade, decoding quality can be set by software parameters, and versatility is good. Hardware system structure The hardware block diagram of DSP MP3 decoding system is shown in Figure 1. We use low-power DSP chip TMS32VC5416 for software decoding, 32M CF card as the medium for storing MP3 files, and USB interface as communication interface with PC to transmit data. Fast speed, can download and upload MP3 on PC, programmable logic device CPLD (select EPM7128SL84) is used to generate chip selection of CF card and USB interface chip and control its reading and writing. TMS320VC5416 fixed point DSP TI's TMS320VC5416 fixed-point arithmetic digital signal processor (DSP), which has low power consumption and high performance, uses an improved Harvard bus structure: a program bus, three data buses, and a data bus width of 16 bits. Separate data and instruction space allows the chip to have a high degree of parallelism, allowing simultaneous access of instructions and data in a single cycle, coupled with its highly optimized instruction set, making the chip highly computationally fast, up to Up to 160MIPS. Audio transmission and playback system Introduction of TLV320AIC23 D/A adopts TLV320AIC23 chip. TLV320AIC23 (hereinafter referred to as AIC23) is a high-performance stereo audio Codec chip with built-in headphone output amplifier. It supports MIC and LINEIN input modes (two choices), and has both input and output. Programmable gain adjustment. AIC23's analog-to-digital conversion (ADCs) and digital-to-analog conversion (DACs) components are highly integrated inside the chip, using advanced Sigma-delta oversampling technology to sample 20, 24bit and 32bit in the 8K to 96K frequency range. The output signal-to-noise ratio of the ADC and DAC can reach 90dB and 100dB, respectively. At the same time, the AIC23 also has very low power consumption, with a power of only 23mW in playback mode and less than 15uW in power-saving mode. Thanks to the above advantages, the AIC23 is an ideal audio analog I/O device. Digital audio interface design of AIC23 and DSP DSP and AIC23 are connected as shown in Figure 2. The clock frequency output 12M of the PDIUSBD12 programmable by the USB1.1 interface device is used as the clock input CLK12M of the stereo audio Codec chip AIC23. The AIC23's configuration interface supports IαC mode and SPI mode. The system uses a DSP's McBSP to connect to AIC23 in SPI mode. The DSP is configured in master mode and the AIC23 is configured in slave mode. The AIC23 outputs serial data. The DSP's MCBSP serial port has six pins that connect the data path and control path to the AIC23. The data is transmitted by BDX0 and BDR0, and the control of the synchronization signal is realized by BFSX0, BFSR0, and BCLKX0. The digital audio interface adopts the DSP mode, which is compatible with the MCBSP serial port of TI's DSP. The timing of this mode is shown in Figure 3. It is known from the figure that data transmission starts at the falling edge of the LRCIN/LRCOUT signal, first left channel data transmission, then right channel data transmission. The DSP needs to process the data from and to the AIC23 to achieve the acquisition and playback of the sound. McBSP communicates with the CPU in DMA mode, receives or sends a group of units through DMA, and then gives the CPU a break. In the DMA mode, each time the serial port sends or receives a unit, it will automatically trigger the DMA to transfer it to an internal Buffer. When the Buffer is full, it will tell the CPU to process through the interrupt. In the DMA interrupt service program, in order to be reliable, the data of this Buffer can be copied to another space to be processed, that is, two-stage Buffer, and then the flag is set, and the CPU queries the flag in the main program and then performs corresponding processing. Buffers for DMA operations can be configured through registers. USB interface implementation USB interface uses high-performance, parallel bus USB interface device PDIUSBD12 (hereinafter referred to as D12), D12 conforms to the universal serial bus USB1.1 version specification, can realize high-speed parallel interface with DSP microcontroller, D12 and DSP connection as shown in Figure 4. Show. The chip selects D12 from the CPLD and controls the reading and writing of D12; ALE is connected to the low level to indicate an independent address and data bus configuration; the A0 pin of D12 is connected to the A0 of the DSP to control the command and data status of the D12. CF card interface design The CF card is a small, large-capacity, low-power, intelligent storage medium that is widely used in portable devices. FlashMemory (flash memory) is the main carrier, and internal microprocessor is used for timing control and storage management. The CF card is connected to the DSP as shown in Figure 5. A3~A0 of the CF card are data, command, or status register address lines. D15~D0 are data buses, which can be accessed by 16 or 8 bits. When the chip select signals CE1# and CE2# are low at the same time, they are 16 bits. Access format; when CE1# is set high and CE2# is low, it is 8-bit access format. There are three access modes of CF: Memory mode, I/O mode, TrueIDE mode. The CF card working mode in this system selects the default mode of power-on, namely: Memory mode, chip select CE1#, CE2# by programmable logic device EPM7128SL84 The 8-bit address A15~A22 of the DSP is decoded. CF card working voltage is 5V or 3.3V, the design uses 3.3V working voltage, which is convenient for data output and address can be directly connected with DSP. DSP implementation of MP3 decoding MP3 file format MP3 is one of the most popular audio formats in the world, and it uses the MPEG-1III layer standard compression encoding format. Music that follows the MP3 standard has a high compression ratio and high fidelity, and its compression ratio can reach 1:10~12, that is, 1 minute CD quality music can be compressed to 1 megabyte after being compressed by MP3. Basically not true. MP3 has a high compression ratio and a small distortion, but its algorithm is also complicated. The content of the MP3 file is an audio bit stream data file, which is composed of several data frames, and the structure of each data frame is as shown in FIG. 6. The audio data in each frame contains sampling information of 1152 original audio signals and is formed by Huffman coding. The other contents of the data frame are: Header information: A portion of an audio bitstream that contains synchronization and status information. Check Word: A portion of the audio bitstream that contains information for error detection. Auxiliary information: A portion of an audio bitstream that contains relevant information that can be used for decoding in each frame. Scaling factor information: A portion of an audio bitstream that contains information used to calculate the audio data quantization scale factor. Huffman encoded data: A portion of an audio bitstream that contains Huffman encoding of all raw audio sample data in each frame. Additional data: A portion of an audio bitstream that can contain a series of user-defined auxiliary data. MP3 decoding Layer III uses a more complex bitstream structure. The flowchart of the decoding program is shown in Fig. 7. First, the synchronization word of each frame is obtained, and the header information is obtained, thereby obtaining each corresponding parameter, and the actual one-frame audio data is obtained according to the parsing of the header information. Reading the main data to obtain the scale factor data, decoding the sample, and then inverting the decoded sample order. If the block type (BlockSplit_type) and the flag type (Flag_typ) are both 1, the samples are reordered according to the side information. The selection information of the Fuman codebook is subjected to Huffman decoding, and then inverse quantization is performed, and the inverse quantization result is stereo processed according to the stereo information of the frame header. Finally, the digital audio signal is reconstructed by the aliasing process, the IMDCT, and the synthesis filter. Conclusion The system uses a high-performance chip and an excellent analog interface. It has strong signal processing capability and can perform stereo decoding algorithms with high quality. On the basis of the system's hardware and software, the display and keyboard, etc., can add a user interface. The system can be integrated into digital cameras and other products to increase the MP3 player function, and has broad application prospects. Pvc Luggage Tag,Unique Luggage Tags,Shaped Luggage Tag Clover Trading Co., Ltd , http://www.zjflashlight.com