March 29, 2024

LSI package development

Market trends in LSI packaging

The world's electronic information equipment market, be summed up by LSI package, as shown, total deliveries increased 1 turn in 2003, followed by increases along by the year 2005 is expected to reach in 2001 1.5 times the size.

In terms of package form, surface mounts represented by SOP ( small outline package ) and QFP ( four-sided flat package ) are in the mainstream, accounting for the overwhelming proportion. This trend is almost unchanged in 2005 . In terms of growth rate, 2005 is expected to increase by 50% compared with 2001 .

In contrast, the pin-inserted package represented by DIP ( Dual In-Line Package ) accounted for only 10% of the total in 2002 , but the trend of gradual reduction has continued, and will shrink to around 6% by 2005 . On the other hand, in a BGA (ball grid array) or CSP (chip scale package) as the representative of area array packages show a greater growth rate after 2002, the year 2005 will be three times the size of 2001, reaching All packages have a 10% or more share.

In addition to the above, it is expected that there will be a significant increase in the 3D form of SiP package ( system package ) . In 2001 , it was almost impossible to get statistics, but in 2005 it will reach 5 times the size of 2001 , accounting for more than 3% of the entire package .

Figure 1   Variety of package form demand changes and forecasts

Figure 2   Changes in LSI package form

LSI encapsulation technology evolution

Overall analysis

The continuous improvement of the thermoelectric performance of system products, especially the high frequency and high pin count requirements, has led to the packaging technology from the traditional peripheral lead package to the surface array package, that is, the pin insertion type progresses to the surface mount, and then from the SCP ( single Chip packaging ) progressed to SiP . The new package form is available, but it does not mean that the past package is immediately replaced and disappeared. For a considerable period of time, the past package form is still in the mainstream. Even today, the SOP and QFP of the surrounding pin package still account for the majority. The technical changes in various package types are shown in Figure 2 .

Early DIP package pins were located on both sides of the IC and were used for devices with fewer than 64 pins , including various memories and microcontrollers. After the surface mount pins is divided into both sides of the SOP and IC pinout around the IC in the LCC (leaded / leadless chip carrier) and QFP form. SOP is used for devices with less than 64 pins , including TSOP ( Thin Small Outline Package ) , TSSOP ( Thin Micro Reduced Package ) , SSOP ( Micro Reduced Package ) , SOJ ( Small Outline J Type) Feet ) and so on. QFP is commonly used in high pin count packages for ASICs , logic ICs, and a variety of low- to mid- range devices with pin counts ranging from 36-208 and 212-304 .

In order to cope with the increasing number of IC pins and the trend of thinner and lighter devices, the BGA package form of solder balls and boards was developed after the 1990s , and FPBGA ( fine pitch BGA) , CSP , FCP ( Flip Chip Package ) , WLP ( Wafer Level Package ) , TCP ( Tape Tape Package ) , and high-end packaging technologies such as MCP ( multi-chip package ) and SiP that combine multiple wafers in combination with multiple package technologies To meet the CPU , PC chipset, graphics chip, FPGA , ASIC chip high efficiency, high speed, high integration, high I / O number, environmental protection, power saving and other needs.

BGA package is suitable for high pin count IC products, mainly for SoC , graphics chipset, FPGA , wireless communication and other application chips, especially the I/O number exceeds 300. The traditional pin-insertion package can not meet the demand. BGA package The market is thus expanding.

CSP is suitable for low pin count ICs . The packaged IC area is no more than 1.2 times larger than the bare chip size . The advantages of CSP are small and thin, which can provide good heat dissipation. It is mainly used in DRAM , SRAM , Flash and other memory products. In particular , the new device DDR II extended by SDRAM is super high speed, small size, high capacity development, and CSP is the standard package form. The traditional TSOP package can not support its basic architecture and must be transformed into CSP .

Three major technology trends

Flip Chip technology is a typical wafer-level package, a chip bumps (Bump) and the substrate (Substrate) in place of the wire bonding connection (wire bonding) technique, for I / O number of the above product in 1000, its advantage lies in its ability Significantly improve the electrical and thermal performance of the product. Flip Chip is suitable for high pin count, high speed, multi-function devices such as high performance MCU , MPU , ASIC , RF , high-end DSP , SoC , graphics chipset with communication, Internet access, wireless transmission, digital image processing, GPS function Etc., the application level is very extensive. However, its entry threshold is high, and technology winners can take advantage of the market.

The traditional IC packaging process is to cut the wafer into a bare chip and then perform the sealing. The WLP simplifies the above process and directly packages and tests the entire wafer before cutting into a single die. There is no need to go through any packaging steps in the middle, which significantly reduces the size of the IC and greatly reduces the cost of packaging. The advantage of WLP is that since the solder ball is only separated between the chip and the circuit board, the circuit transmission path can be shortened, and the inductance and the capacitance are reduced, so that the current loss and the probability of electromagnetic wave interference can be effectively reduced, thereby improving the working efficiency of the circuit. Because of the lack of plastic or ceramic packaging of the IC external seal, the heat loss generated by the IC chip can be directly radiated from the back of the chip by heat conduction and heat radiation, which can effectively solve the heat dissipation problem of the mobile electronic device. Currently, portable electronic products such as mobile phones, PDAs , notebook computers, digital cameras and MP3 players are benefiting from WLP technology. Applications are concentrated in three areas, namely low I/O number ICs ( such as analog, RF, power amplifier, power devices ) , memory (EEPROM , Flash) and passive components. In the future market development, in addition to the continuous increase of low pin count devices, the application of high-speed devices such as memory will continue to develop.

At present, the development of SoC faces bottlenecks and challenges. For example , the cost of a mask of 0.13 micron is more than 1 million US dollars. On the other hand, the narrower the process spacing, the larger the leakage current of the gate, and the difficulty of speeding up after miniaturization. Because SiP remains independent between the various components in the package, it avoids the difficulties in integrating the analog and digital circuits in the SoC design, reduces the complexity of the circuit design, shortens the design time, and ensures the yield. Therefore, when SoC technology is not yet mature, SiP has good development opportunities and will become the first choice of many system vendors.

In the past, the SiP technology was mainly based on the 2D form in which a plurality of bare chips combined into a system were placed on the same substrate plane , and the way to connect the IC to the substrate was to perform wire bonding, flipping, and tape automatic bonding. (Tape Automated Bonding , TAB) and other technologies, this type of package still has various shortcomings such as long circuit transmission path and large package size. The previous MCM ( multi-chip module ) package is a SiP case in the form of a 2D plane . The MCM is to place a plurality of ICs on the same substrate plane and then connect them to each other by wire bonding. However, in addition to the above disadvantages of the long transmission path and the difficulty in shrinking the package size, such a package form has difficulty in controlling the yield. In order to improve the above disadvantages, the current SiP is gradually moving toward the trend of stacking and packaging the chips in 3D . 3D stack package is divided into two, the first one directly after the stacked die and connected to the substrate, then encapsulated (chip stacked), another plurality of packaged chips sucked and then combined together after stacking (package stacked ) . The former packaging method can only overlap four layers of bare chips at most, and it has difficulty in testing. At present, the 3D form of SiP is still based on the latter package stacked , which not only has the advantages of pre-testing, but also the number of layers that can be stacked. There are also many, and can meet the needs of light, thin and short.